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functional block diagram ll dl clk dr lr dgnd v l nrl agnd nrr v s 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 ad1866 16-bit dac 16-bit dac 16-bit serial register 16-bit serial register v b l v o r v s v b r v ref v ref v o l rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a single supply dual 16-bit audio dac ad1866* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features dual serial input, voltage output dacs single +5 volt supply 0.005% thd+n low power C50 mw 115 db channel separation operates at 8 3 oversampling 16-pin plastic dip or soic package applications multimedia workstations pc audio add-in boards portable cd and dat players automotive cd and dat players noise cancellation product description the ad1866 is a complete dual 16-bit dac offering excellent performance while requiring a single +5 v power supply. it is fabricated on analog devices abcmos wafer fabrication process. the monolithic chip includes cmos logic elements, bipolar and mos linear elements and laser trimmed, thin- film resistor elements. careful design and layout techniques have resulted in low distortion, low noise, high channel separa- tion and low power dissipation. the dacs on the ad1866 chip employ a partially segmented architecture. the first three msbs of each dac are segmented into 7 elements. the 13 lsbs are produced using standard r-2r techniques. the segments and r-2r resistors are laser trimmed to provide extremely low total harmonic distortion. the ad1866 requires no deglitcher or trimming circuitry. each dac is equipped with a high performance output ampli- fier. these amplifiers achieve fast settling and high slew rate, producing 1 v signals at load currents up to 1 ma. the buff- ered output signal range is 1.5 v to 3.5 v. the 2.5 v reference voltages eliminate the need for false ground networks. a versatile digital interface allows the ad1866 to be directly connected to all digital filter chips. fast cmos logic elements allow for an input clock rate of up to 16 mhz. this allows for operation at 2 , 4 , 8 , or 16 the sampling frequency (where f s = 44.1 khz) for each channel. the digital input pins of the ad1866 are ttl and +5 v cmos compatible. * protected by u.s. patent nos: 3,961,326; 4,141,004; 4,349,811; 4,857,862; and patents pending. the ad1866 operates on +5 v power supplies. the digital supply, v l , can be separated from the analog supply, v s , for re- duced digital feedthrough. separate analog and digital ground pins are also provided. in systems employing a single +5 volt power supply, v l and v s should be connected together. in bat- tery operated systems, operation will continue even with re- duced supply voltage. typically, the ad1866 dissipates 50 mw. the ad1866 is packaged in either a 16-pin plastic dip or a 16-pin plastic soic package. operation is guaranteed over the temperature range of C35 c to +85 c and over the voltage supply range of 4.75 v to 5.25 v. product highlights 1. single supply operation @ +5 v. 2. 50 mw power dissipation. 3. thd+n is 0.005% (typical). 4. signal-to-noise ratio is 95 db (typical). 5. 115 db channel separation (typical). 6. compatible with all digital filter chips. 7. 16-pin dip and 16-pin soic packages. 8. no deglitcher required. 9. no external adjustments required.
rev. 0 C2C ad1866Cspecifications (t a = +25 8 c and +5 v supplies unless otherwise noted) min typ max unit resolution 16 bits digital inputs v ih 2.4 v v il 0.8 v i ih , v ih = v l 1.0 m a i il , v il = dgnd C10.0 m a maximum clock input frequency 13.5 mhz accuracy gain error 3 % of fsr gain matching 3 % of fsr midscale error 30 mv midscale error matching 10 mv gain linearity error 3db drift (0 c to +70 c) gain drift 100 ppm/ c midscale drift C130 m v/ c total harmonic distortion + noise 0 db, 990.5 hz AD1866N 0.005 0.01 % ad1866r 0.005 0.01 % C20 db, 990.5 hz AD1866N 0.02 % ad1866r 0.02 % C60 db, 990.5 hz AD1866N 2.0 % ad1866r 2.0 % channel separation (1 khz, 0 db) 108 115 db signal-to-noise ratio (with a-weight filter) 95 db d-range (with a-weight filter) 90 db output voltage output pins (v ol , v or ) output range ( 3%) 1v output impedance 0.1 w load current 1ma bias voltage pins (v bl , v br ) output range +2.5 v output impedance 350 w power supply specification, v l and v s 4.75 5 5.25 v operation, v l and v s 3.5 5.25 v +i, v l and v s = 5 v 10 14 ma power dissipation 50 70 mw temperature range operation C35 85 c storage C60 100 c specifications subject to change without notice. specifications in boldface are tested on all production units at final electrical
typical performanceCad1866 rev. 0 C3C ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 20500 5500 500 15500 10500 frequency ?hz thd+n ?db ?0db ?0db 0db figure 1. thd+n vs. frequency 125 120 123 121 10 3 122 10 2 124 10 4 frequency ?hz channel separation ?db 10 5 figure 2. channel separation vs. frequency ?0db supply voltage thd+n ?db 0db ?0 ?00 5.6 ?0 ?0 4.6 ?0 4.4 ?0 ?0 ?0 5.4 5.2 5.0 4.8 ?0db figure 3. thd+n vs. supply voltage input amplitude ?db gain linearity error ?db 6 ? 20 ? ? ?0 ? ?00 4 0 2 0 ?0 ?0 ?0 125? ?5? 0? 25? 70? figure 4. gain linearity error vs. input amplitude temperature ?? thd+n ?db ?0 ?00 125 ?0 ?0 ?0 ?0 ?5 ?0 ?0 ?0 100 75 50 25 0 ?5 ?0db ?0db 0db figure 5. thd+n vs. temperature frequency ?hz psrr ?db 80 40 10 3 10 5 70 50 10 4 60 figure 6. power supply rejection ratio vs. frequency (supply modulation amplitude at 500 mv p-p)
ad1866 rev. 0 C4C absolute maximum ratings* v l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6 v v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v digital inputs to dgnd . . . . . . . . . . . . . . . . . . . C0.3 v to v l soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1866 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configuration ll dl clk dr lr dgnd v l nrl agnd nrr v s 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 ad1866 16-bit dac 16-bit dac 16-bit serial register 16-bit serial register v b l v o r v s v b r v ref v ref v o l pin designations pin mnemonic description 1 1v l digital supply (+5 v) 1 2 ll left channel latch enable pin 1 3 dl left channel data input pin 1 4 clk clock input pin 1 5 dr right channel data input pin 1 6 lr right channel latch enable pin 1 7 dgnd digital common pin 1 8v b r right channel bias pin 1 9v s analog supply (+5 v) 10 v o r right channel output pin 11 nrr right channel noise reduction pin 12 agnd analog common pin 13 nrl left channel noise reduction pin 14 v o l left channel output pin 15 v s analog supply (+5 v) 16 v b l left channel bias pin ordering guide temperature package package model range description option AD1866N C35 c to +85 c plastic dip n-16 ad1866r C35 c to +85 c soic r-16 ad1866r-reel C35 c to +85 c soic r-16
total harmonic distortion + noise total harmonic distortion plus noise (thd+n) is defined as the ratio of the square root of the sum of the squares of the am- plitudes of the harmonics and noise to the amplitude of the fun- damental input frequency. it is usually expressed in percent (%) or decibels (db). d-range distortion (eiaj specification) d-range distortion is the ratio of the amplitude of the signal at an amplitude of C60 db to the amplitude of the distortion plus noise. in this case, an a-weight filter is used. the value speci- fied for d-range performance is the ratio measured plus 60 db. signal-to-noise ratio the signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full-scale output is present to the ampli- tude of the output with no signal present. it is expressed in decibels (db) and measured using an a-weight filter. gain linearity gain linearity is a measure of the deviation of the actual output amplitude from the ideal output amplitude. it is determined by measuring the amplitude of the output signal as the amplitude of that output signal is digitally reduced to a lower level. a per- fect d/a converter exhibits no difference between the ideal and actual amplitudes. gain linearity is expressed in decibels (db). midscale error midscale error, or bipolar zero error, is the deviation of the ac- tual analog output from a voltage at the bias pin when the twos complement input code representing midscale is loaded in the dac. midscale error is expressed in mv. functional description the ad1866 is a complete, monolithic dual 16-bit digital audio dac which runs off a single +5 volt supply. as shown in the block diagram, each channel contains a voltage reference, a 16-bit serial-to-parallel input register, a 16-bit input latch, a 16-bit dac, and an output amplifier. the voltage reference section provides a reference voltage and a false ground voltage for each channel. the low noise bandgap circuits produce reference voltages that are unaffected by changes in temperature, time, and power supply. the input registers are fabricated with cmos logic gates. these gates allow high switching speeds and low power con- sumption, contributing to the fast digital timing, the low glitch and low power dissipation of the ad1866. ll dl clk dr lr dgnd v l nrl agnd nrr v s 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 ad1866 16-bit dac 16-bit dac 16-bit serial register 16-bit serial register v b l v o r v s v b r v ref v ref v o l ad1866 functional block diagram the 16-bit dac uses a combination of segmentation and r-2r architecture to achieve good integral and differential linearity. the resistors which form the ladder structure are fabricated with silicon-chromium thin film. laser trimming of these resis- tors further reduces linearity error, resulting in low output distortion. the output amplifier uses both mos and bipolar devices and incorporates an npn class a output stage. it is designed to pro- duce high slew rate, low noise, low distortion, and optimal fre- quency response. rev. 0 C5C definition of specificationsCad1866
grounding recommendations the ad1866 has two ground pins, designated as agnd (pin 12) and dgnd (pin 7). the analog ground, agnd, serves as the high quality reference ground for analog signals and as a return path for the supply current from the analog portion of the device. the system analog common should be located as close as possible to pin 12 to minimize any voltage drop which may develop between these two points, although the internal circuit is designed to minimize signal dependence of the analog return current. the digital ground, dgnd, returns ground current from the digital logic portion of the device. this pin should be connected to the digital common node in the system. as shown in figure 7, the analog and digital grounds should be joined at one point in a system. when these two grounds are connected such as at the power supply ground, care should be taken to minimize the voltage difference between the dgnd and agnd pins in or- der to ensure the specified performance. power supplies and decoupling the ad1866 has three power supply input pins. v s (pins 9 and 15) provide the supply voltages which operate the analog por- tion of the device including the 16-bit dacs, the voltage refer- ences, and the output amplifiers. the v s supplies are designed to operate from a +5 v supply. these pins should be decoupled to the analog ground using a 0.1 m f capacitor. good engineer- ing practice suggests that the bypass capacitor be placed as close as possible to the package pins. this minimizes the inher- ent inductive effects of printed circuit board traces. v l (pin 1) operates the digital portions of the chip including the input shift registers and the input latching circuitry. v l is also designed to operate from a +5 v supply. this pin should be by- passed to digital common using a 0.1 m f capacitor, again placed as close as possible to the package pins. figure 7 illustrates the correct connection of the digital and analog supply bypass capacitors. an important feature of the ad1866 audio dac is its ability to operate at diminished power supply voltages. this feature is very important in portable battery operated systems. as the bat- teries discharge, the supply voltage drops. unlike any other au- dio dac, the ad1866 can continue to function at supply voltages as low as 3.5 v. because of its unique design, the power requirements of the ad1866 diminish as the battery volt- age drops, further extending the operating time of the sys tem. power supply 4.7? 4.7? (capacitor values are 0.1 ? unless otherwise indicated) 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 nrl agnd nrr ad1866 ll dl clk dr lr dgnd v b r v b l + + v s v o l v l v o r v s figure 7. recommended circuit schematic noise reduction capacitors the ad1866 has two noise reduction pins, designated as nrl (pin 13) and nrr (pin 11). in order to meet specifications, it is required that external noise reduction capacitors be con- nected from these pins to agnd to reduce the output noise contributed by the voltage reference circuitry. as shown in fig- ure 7, each of these pins should be bypassed to agnd with a 4.7 m f or larger capacitor. the connections between the ca- pacitors, package pins and agnd should be as short as pos- sible to achieve the lowest noise. using v b l and v b r the ad1866 has two bias voltage reference pins, designated as v b r (pin 8) and v b l (pin 16). each of these pins supplies a dc refe rence voltage equal to the center of the output voltage swing. these bias voltages replace false ground networks previously required in single supply audio systems. at the same time, they allow dc coupled systems, improving audio performance. ad1866Canalog circuit considerations rev. 0 C6C
+ 5v + 5v + 5v false ground (2.5v) v o r v o l v o r v o l figure 8a. schematic using false ground figure 8a illustrates the traditional approach used to generate false ground voltages in single supply audio systems. this cir- cuit requires additional power and circuit board space. the ad1866 eliminates the need for false ground circuitry. v b r and v b l generate the required bias voltages previously generated by the false ground. as shown in figure 8b, v b r and v b l may be used as the reference point in each output channel. this permits a dc coupled output signal path. this eliminates ac coupling capacitors and improves low frequency performance. it should be noted that these bias outputs have relatively high output impedance and will not drive output cur- rents larger than 100 m a without degrading the specified perfor mance. analog circuit considerationsCad1866 rev. 0 C7C +5v +5v 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 nrl agnd nrr ad1866 ll dl clk dr lr dgnd v o l v o r v o r v s v b r v o l v s v l v b l figure 8b. circuitry using voltage biases distortion performance and testing the thd+n figure of an audio dac represents the amount of undesirable signal produced during reconstruction and play- back of an audio waveform. therefore, the thd+n specifica- tion provides a direct measure to classify and choose an audio dac for a desired level of performance. figure 1 illustrates the typical thd+n versus frequency performance of the ad1866. it is evident that the thd+n performance of the ad1866 re- mains stable at all three amplitude levels through a wide range of frequencies. a load impedance of at least 2 k w is recom- mended for best thd+n performance. analog devices tests all ad1866s on the basis of thd+n per- formance. during the distortion test, a high speed digital pat- tern generator transmits digital data to each channel of the device under test. sixteen-bit data is latched into the dac at 352.8 khz (8 f s ). the test input code is a digitally encoded 990.5 hz sine wave with 0 db, C20 db, and C60 db amplitudes. a 4096 point fft calculates total harmonic distortion + noise, signal-to-noise ratio, and d-range. no deglitchers or external adjustments are used.
ad1866Cdigital circuit considerations rev. 0 C8C l s b m s b m s b l s b clk dl dr ll lr figure 9. ad1866 control signals input data the digital input port of the ad1866 employs five signals: data left (dl), data right (dr), latch left (ll), latch right (lr), and clock (clk). dl and dr are the serial inputs for the left and right dacs, respectively. input data bits are clocked into the input register on the rising edge of clk. the falling edges of ll and lr cause the last 16 bits which were clocked into the serial registers to be shifted into the dacs, thereby up- dating the respective dac outputs. for systems using only a single latch signal, ll and lr may be connected together. for systems using only one data signal, dr and dl may be con- nected together. data is transmitted to the ad1866 in a bit stream composed of 16-bit words with a serial, twos comple- ment, msb first format. left and right channels share the clock (clk) signal. figure 9 illustrates the general signal requirements for data transfer for the ad1866. timing figure 10 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished prop- erly. the input pins of the ad1866 are both ttl and +5 v cmos compatible. >30ns >10ns >10ns >30ns >30ns >15ns >40ns >40ns dr/dl clk lr/ll >67ns >40ns figure 10. ad1866 input signal timing the maximum clock rate of the ad1866 is specified to be at least 13.5 mhz. this clock rate allows data transfer rates of 2 , 4 , 8 , and 16 f s (where f s equals 44.1 khz). the applica- tions section of this data sheet contains additional guidelines for using the ad1866.
rev. 0 C9C in summary, the ad1866 is an excellent choice for multimedia, battery operated portable or automotive digital audio systems. in the following sections, some examples of high performance audio applications featuring the ad1866 are described. ad1866 with the sony cxd2550p digital filter figure 11 illustrates a 16-bit cd player design incorporating an ad1866 dac, a sony cxd2550p digital filter, and 2-pole antialias filters. this high performance, single supply design op- erates at 8 f s and is suitable for portable and automotive ap- plications. in this design, the cxd2550p filter transmits left and right channel digital data to the ad1866. the left and right latch signals, ll and lr, are both provided by the word clock signal (lrcko) of the digital filter. the digital data is con- verted to low distortion output voltages by the output amplifiers on the ad1866. also, no deglitching circuitry or external ad- justments are required. b ypass capacitors, noise reduction capacitors and the antialias filter details are omitted for clarity. additional applications in addition to cd player designs, the ad1866 is suited for similar applications such as dat, portable musical instruments, laptop and notebook personal computers, and pc audio i/o boards. the circuit techniques illustrated here are directly ap- plicable in those applications. figures 12, 13, 14, and 15 show connection diagrams for the ad1866 and several popular digital filter chips from npc and yamaha. each application operates at 8 f s operation. please refer to the appropriate sections of this data sheet for additional information. applications of the ad1866 the ad1866 is a high performance audio dac specifically de- signed for portable and automotive digital audio applications. these market segments have technical requirements fundamen- tally different than those found in the high-end or home use market segment. portable equipment must rely on components which require low amounts of power to offer reasonable play- back times. also, battery voltage tends to diminish as the end of the discharge cycle is approached. the ad1866s ability to op- erate from a single +5 v supply makes it a good choice for bat- tery operated gear. and, as the battery voltage drops, the power dissipation of the ad1866 drops. this extends the usable bat- tery life. finally, as the battery supply voltage drops, the bias voltages and signal swings also drop, preventing signal clipping and abrupt degradation of distortion. figure 3 illustrates how the thd+n performance of the ad1866 remains constant through a wide supply voltage range. automotive equipment relies on components which are able to consistently perform over a wide range of temperatures. in addi- tion, due to the limited space available in automotive applica- tions, small size is essential. the ad1866 has guaranteed operation between C35 c and +85 c, and the 16-pin dip or 16-pin soic package is particularly attractive where overall size is important. since the ad1866 provides dc bias voltages, the entire signal chain can be dc coupled. this eliminates ac coupling capacitors from the signal path, improving low frequency performance and lowering system cost and size. 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 8 7 6 5 2 3 1 4 +5v power supply left channel output right channel output ad1866 ll dl clk dr lr dgnd 1 2 3 4 5 6 7 8 9 18 10 15 14 12 11 16 17 13 test cxd2550p lrck slot datar bcko latch datal lrcko v dd nrl agnd nrr 1000 pf 6.8k w 330 pf njm2100 1000 pf 330 pf v ss v ss v l v s v b l v o l v o r v b rv s +v s 6.8k w 6.8k w 6.8k w 6.8k w 6.8k w figure 11. ad1866 with sony cxd2550p digital filter applications of the ad1866
ad1866 rev. 0 C10C 20 1 2 3 4 5 6 7 8 10 11 12 13 14 28 27 26 25 24 23 22 21 19 18 16 15 17 bcko wcko dol dor ow18 ow20 sm5813 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 low- pass filter left channel output right channel output +5v power supply ad1866 ll dl clk dr lr dgnd nrl agnd nrr 9 low- pass filter cob v o r v b rv s v o l v s v b l v l v dd v ss 2 v ss 1 figure 12. ad1866 with npc sm5813 digital filter 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 low pass filter low pass filter left channel output right channel output 1 2 3 4 5 6 7 8 15 14 13 12 11 10 16 9 bcko wdco dor dol sm5818ap omod1 +5v power supply ad1866 ll dl clk dr lr dgnd nrl agnd nrr v o l v s v b l v b r v l v s v ss v dd v o r figure 13. ad1866 with npc sm5818ap digital filter
applicationsCad1866 rev. 0 C11C 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 v r b low- pass filter left channel output right channel output +5v power supply ad1866 ll dl clk dr lr dgnd nrl agnd nrr v o l 1 2 3 4 5 6 7 8 15 14 13 12 11 10 16 9 low- pass filter v 2 dd 16 / 18 st bco wco dro dlo ym3434 v ss v dd 1 v o r v s v b l v s v l figure 14. ad1866 with yamaha ym3434 digital filter 15 14 13 12 11 10 16 9 1 2 3 4 5 6 8 7 low- pass filter left channel output right channel output +5v power supply bcko di n bck o vd d wck o do l d g do r 10 10 15 14 13 12 11 16 17 18 1 2 3 4 5 6 7 8 9 ow20 wcko dol dor sm5840a/b bcko low- pass filter v ss v dd ad1866 ll dl clk dr lr dgnd nrl agnd nrr v o r v o l v s v b l v l v s v b r figure 15. ad1866 with npc sm5840c digital filter
ad1866 rev. 0 C12C outline dimensions dimensions shown in inches and (mm). c1590C10C12/91 printed in u.s.a. plastic dip (n) package 0.125 (3.18) min 0.035 (0.89) 0.18 (4.57) 0.3 (7.62) 0.87 (22.1) max 0.25 (6.35) 0.31 (7.87) 0.18 (4.57) max 0.011 (0.28) 18 9 16 0.018 (0.46) 0.033 (0.84) 0.1 (2.54) plastic soic (r) package 0.042 (1.07) 0.013 (0.32) 0.019 (0.49) 0.05 (1.27) ref 0.104 (2.65) 0.012 (0.3) 1 8 9 16 0.413 (10.50) 0.419 (10.65) 0.299 (7.60) 0.030 (0.75)

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